1. Field of the Invention
The present invention relates generally to analog-to-digital converters, and more specifically, to an on-chip system including an analog-to-digital converter (ADC) that is operated by a clock signal derived from the same master clock that operates digital circuits.
2. Background of the Invention
System-on-Chip (SoC) integrated circuits are ubiquitous in embedded applications such as household devices, personal computers and industrial electronics. SoCs reduce the cost of systems and increase their performance by reducing the parts count and decreasing the number of interconnects required to implement a given device. SoCs frequently include analog conversion components such as ADCs and digital-to-analog converters (DACs) in order to provide a system interface to analog signals, perform analog measurements and to provide analog outputs.
In an SoC design, the ADC typically coexists with a large amount of digital logic, which typically implements a processor core or a dedicated signal processing circuit. Such circuits generate a large amount of switching noise on power supply rails of the integrated circuit, as well as generating noise on signal lines within the ADC portion of the integrated circuit that affect the converter output values. Further, the SoC may include power converters such as charge pump circuits that switch large currents, increasing the amount of noise in the ADC measurements. The noise level at the ADC input affects the useful resolution of the converter and is typically manageable only by adjusting the circuit layout and “managing” the timing of the digital switching signals so that all of the transitions occur over a small portion of the ADC conversion cycle. The highest frequency digital circuit clocks are typically the signals that are managed, as those clocks are responsible for the majority of the noise generated in the analog circuits.
However, digital circuits such as processors, which are affected by program flow as well as clock state, cannot be managed in the manner described above, as logic transitions can and will occur at any point in the ADC conversion cycle. Further, when a processor core instruction rate is much higher than the converter sample rate, the various phases of instruction processing will lie throughout the conversion cycle and cannot be held to just a small window without affecting performance of the core.
Therefore, it would be desirable to provide an SoC including an ADC that can be operated in a manner that reduces or eliminates the noise generated during analog signal conversions by a processor core or other digital circuit as well as power conversion circuits.